FIELD OF THE INVENTION
The invention lies in the semiconductor technology field. More specifically, the present invention relates to a burn-in test device for semiconductor memories, having a test board ("test field"), in which there are provided a multiplicity of test receptacles for receiving at least one semiconductor module each. It is thereby possible for burn-in pulses to be applied to each semiconductor module and for each semiconductor module to be switched off via a separate terminal.
Burn-in tests are carried out in order to sort out and reject poor semiconductor modules before the latter are incorporated into circuits. Burn-in pulses or signals are thereby applied to the inputs of the semiconductor modules under harder operating conditions than occur during normal operation of the semiconductor module. In other words, the burn-in tests are carried out under higher temperatures than the normal temperatures for the semiconductor modules and with higher operating voltages than the normal operating voltages.
Burn-in tests are preferably performed on semiconductor memories. There exist, as is known, memories with different layout organizations, such as, for example, 64M DRAMs with the organizations 4M.times.16, 8M.times.8 and 16M.times.4. The terms ".times.16," ".times.8" and ".times.4" denote the number of input/output terminals, "DQ0, DQ1, DQ2, . . . " of the respective DRAM. "4M, ""8M" and "16M" specify the respective storage capacity. A "4M.times.16" DRAM thus has 16 input terminals to be tested.
The procedure heretofore, then, has been such that different test boards are used depending on the number of input terminals. In other words, a different test board is used to test a memory having the "4M.times.16" organization than the one used to test a semiconductor memory having the "8M.times.8" organization. As an alternative, it is also possible to use a test board which is suitable for semiconductor memories having the highest organization. In that case, however, the utilization of the connection capacity is reduced in the case of semiconductor memories having a lower organization.
A test board has 256 receptacles, for example, which are arranged like a matrix in 16 rows and 16 columns. One module is inserted into each receptacle. In this case, the same modules with ".times.16" or ".times.8" or ".times.4", that is to say semiconductor memories with 16 or 8 or 4 input terminals respectively, are tested in the entire test board in each case.
In this context, input/output terminals are to be understood to mean the terminals via which the cell array is accessed. These terminals (data pins) are designated as "DQ", as has already been indicated above. Other signals are also applied to a semiconductor memory, such as, for example, supply voltage VDD, ground voltage VSS, signals CDQM, WE, RAS, CS, CAS, addresses A1, A2, . . . , addresses WA, control signals LDQM, UDQM, DQM, CLK, CKE etc., the individual semiconductor memories--to enable them to be fitted into the same housing--also having not connected ("NC") pins leading outwards.
FIG. 4 illustrates the layout and operation of a prior art burn-in test device for universal application. Four semiconductor memories are shown here, each of which has 54 pins to which the above-mentioned signals or addresses, etc. are applied. Depending on the organization "16M.times.4", "8M.times.8" and "4M.times.16", respectively 4 or 8 or 16 input/output terminals DQ0, DQ1, DQ2, . . . are present. In this case, a semiconductor module having a lower organization has input/output terminals at the locations or pins at which an input/output terminal of a semiconductor memory having a higher organization is also present. For example, pin 5 is an input/output terminal for all organizations, whereas pin 2 is an input/output terminal only for the ".times.8" and ".times.16" organizations. Pin 13 is an input/output terminal only for the ".times.16" organization.
In the case of these prior art burn-in devices, then, the procedure is such that each input line is contact-connected independently of the organization of the memory to be tested at each receptacle at the same pin, as is shown for pin "5" in FIG. 4. In other words, in the entire board, all for example 256 receptacles are in this case contact-connected at the pin 5 via the same input line. If a semiconductor memory with the ".times.8" or ".times.4" organization is inserted into a test board which is designed for the ".times.16" organization, this leads to doubling or quadrupling of the test time for the former organizations. This is because if a semiconductor memory with the ".times.4" organization is inserted into a receptacle of a test board having the ".times.16" organization, test signals that are not utilized are likewise present at the "NC" terminals. Since the memory having a ".times.4" organization is four times larger than the memory having an ".times.16" organization, the test time is quadrupled.
This disadvantageous quadrupling of the test time has been circumvented heretofore only by keeping a separate test board in store for each organization, that is to say separate test boards for ".times.16", ".times.8" and ".times.4" organizations.